Xilinx LogiCore PCI v3.0 - Manual (Page 48)

48 www.xilinx.com PCI v3.0.151 Getting Started Guide
UG157 August 31, 2005
Chapter 5: Synthesizing a Design R
VHDL
1. Start Synplify and choose File > New, or use the new file icon on the toolbar. The New
dialog box appears.
2. Under File Type, select Project File and enter the project name (flowtest in this example)
and synthesis directory:
<Install Path>/vhdl/example/synthesis
3. Click OK to exit the dialog box and return to the project window.
4. To add source files to the new project, click Add.
The first file (used by any design that instantiates Xilinx primitives) is located in:
<Synplicity Install Path>/lib/xilinx
Figure 5-12: Create a New Project
Figure 5-13: Main Project Window