Rainbow Electronics MAX11008 - Manual (Page 58)

MAX11008
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
58 ______________________________________________________________________________________
FIFO (see the Message Mode section) so that the data
words can be read out through the serial interface. In
message mode the FIFO is eight deep, and does not
overflow.
In ADC/average monitoring mode, the 12-bit ADC con-
version results of each selected channel are copied
into the FIFO so that the conversion results can be read
out through the serial interface (see the
ADC Monitoring
Mode section). Each conversion result includes a 4-bit
channel tag that indicates the source of the conversion
(see Table 24a). In ADC/average monitoring mode the
FIFO is seven deep, and always contains the most
recent seven data items. The oldest data placed into
the FIFO is always read out first.
When in LUT streaming mode, the FIFO register is a
write-only register. In LUT streaming mode, write the
data word that is to be written to the EEPROM into the
FIFO register (see the
LUT Streaming Mode section). In
this mode the FIFO is eight deep, and is prevented
from overflow. Data written to the FIFO when it is full is
ignored.
DATA
BITS
BIT NAME RESET STATE FUNCTION
D[15:12] T_HIST[3:0] 0000
Hysteresis limit bits. The T_HIST[3:0] bits set the temperature hysteresis limits for
both channel 1 and channel 2 for V
GATE_ calculations. See Table 14a.
D[11:0] APC[11:0] NA APC parameter bits.
Table 16a. APC Parameter Register (Valid when APCSRC[1:0] = 00)
NA = Not applicable.
DATA BITS BIT NAME RESET STATE FUNCTION
D[15:12] T_HIST[3:0] 0
Temperature hysteresis limit bits. The T_HIST[3:0] bits set the temperature
hysteresis limits for both channel 1 and channel 2 for V
GATE_
calculations. See
Table 16c. Set APCCOMP_ and TCOMP_ to 0 before T_HIST is changed.
D[11:8] Unused NA —
D7 A_AVGCTL 0
APC parameter bit. Controls the averaging equation for channel 1 and
channel 2. Set A_AVGCLT to 0 for average plus 1/16 difference. Set
A_AVGCLT to 1 for average plus 1/4 difference.
D[6:4] A_LIMIT[2:0] 0
APC difference limiter bits. Set A_LIMIT[2:0] to enable the difference limiter for
channel 1 and channel 2 APC averaging. See Table 16d.
D[3:0] A_HIST[3:0] 0
APC hysteresis limit bits. The A_HIST[3:0] bits set the APC hysteresis limits for
both channel 1 and channel 2 for V
GATE_ calculations. See Table 16e. Set
APCCOMP_ and TCOMP_ to 0 before A_HIST is changed.
Table 16b. APC Parameter Register (Valid when APCSRC[1:0] = 10 or 11)