Rainbow Electronics AT83C26 - Manual (Page 12)

12
7511B–SCR–10/05
AT83C26
RESET pin
The TWI ADDRESS BYTE is sampled on A2/CK and A1/RST after a rising edge on RESET pin.
The delay between the rising edge and the sampling of A2/CK and A1/RST is t1.
The value for t1 is 22 CLK period.
The minimum value for t2 is 40 CLK period. During the t2 time, the TWI bus is not ready to
receive a command.
The CLK period depends on the frequency of the signal on CLK pin.
The RESET pin is an I/O with Open Drain. The host IO pin connected to RESET must be an I/O
with open drain (with external pull-up) or an I/O with internal pull up (without external pull-up).
Figure 3. Timings after reset
BYPASS pin
A high level on this pin activates a low power consumption mode.
At reset, the level on this pin must be fixed (VSS or VCC).
Before to set BYPASS pin, SHUTDOWNA and SHUTDOWNB bits must be set.
If SHUTDOWNA bit is set, DCDCA is switched off.
If SHUTDOWNB bit is set, DCDCB is switched off.
If SHUTDOWNA and SHUTDOWNB bits are set, the regulator is switched off.
If BYPASS pin is at a high level, the bandgaps are switched off.
Smart Card Interfaces
The AT83C26 enables the management of up to 5 smart card interfaces. Due to shared IOs
between SC2 and SC3, the user should choose between a full SC2 interface (with CC4 and
CC8) or SC3 interface.
The SC2_FULL bit in SC2_CFG1 register is used to select the SC2/SC3 interfaces
configuration.
SDA Address byte
RESET
Sampling of TWI address
t1
t2