Rainbow Electronics AT83C26 - Manual (Page 26)

26
7511B–SCR–10/05
AT83C26
the CRSTn signal is not set and the CAPTURE_MSB and CAPTURE_LSB registers contain the
value of the counter at the arrival of the ATR.
If the ATR arrives after the rising edge on CRSTn pin and before the card clock counter over-
flows (65535 clock cycles), the activation sequence completes. The CAPTURE_MSB and
CAPTURE_LSB registers contain the value of the counter at the arrival of the ATR (tc time on
Figure 15).
Figure 15. Software activation with ARTn bit = 1
ISO 7816 constraints: ta = 200 card clock cycles
400 card clock cycles< = tb
400 card clock cycles< = tc < = 40000 card clock cycles
Timer[1-0] reset value is 400.
Warm reset (n=1, 2, 3, 4, 5)
The AT83C26 offers a simple and accurate way to control the CRSTn signal during a warm
reset.
After an activation sequence (cold reset), a warm reset is started with a low level on CRST dur-
ing a define delay (between 40000 and 45000 clock cycles for example).
The ARTn bit, the TIMER_MSB and the TIMER_LSB are used to control CRSTn.
The first step is to load the number of CCLK cycles with CRSTn=0 in TIMER registers.
The warm reset is started by setting ART bit (if ART bit is already set, reset ART before).
CVCCn
CRSTn
CCLKn
tc
tb
ta
CIOn
CARDRSTn bit set
1
2
3
4