Rainbow Electronics AT83C26 - Manual (Page 25)

25
7511B–SCR–10/05
AT83C26
Figure 14. Software activation without automatic control (ARTn bit = 0)
Note:
– It is assumed that initially VCARDn[1:0], CARDCKn, CARDIOn and CARDRSTn bits
are cleared, CKSTOPn and IODISn are set (those bits are further explained in the
registers description)
– The user should check the AT83C26 status and possibly resume the activation
sequence if one TWI transfer is not acknowledged during the activation sequence.
Software activation for SCn (n=1, 2, 3, 4, 5) interfaces and ARTn bit = 1
The following sequence can be applied:
1. Card Voltage is set by software to the required value (VCARDn1:0] bits in
SCn_CFG0 register). This writing starts the DC/DC converter (or LDO).
2. Wait of the end of the DC/DC init (or LDO) with a polling on VCARD_OKn bit or wait
for INT to go Low. When VCARD_OKn bit is set (by hardware), CARDIOn bit should
be set by software.
3. CKSTOPn, IODISn are programmed by software. CKSTOPn bit is reset to have the
clock running. IODISn is reset to enable the transparent mode on CIOn,CC4n,
CC8n.
4. CARDRSTn bit is set by software.
Automatic Reset Transition description:
A 16-bit counter starts when CARDRSTn bit is set. It counts card clock cycles. The CRSTn sig-
nal is set when the counter reaches the TIMER_MSB and TIMER_LSB value which corresponds
to the “tb” time (Figure 15).The counter is reseted when the CRSTn pin is released and it is
stopped at the first start bit of the Answer To Request (ATR) on CIOn pin.
The CIOn pin is not checked during the first 200 clock cycles (ta, Figure 15). If the ATR arrives
before the counter reaches TIMER_MSB and TIMER_LSB values, the activation sequence fails,
CVCCn
CRSTn
CCLKn
CIOn
2
4
3
1
ATR