Rainbow Electronics AT83C26 - Manual (Page 20)

20
7511B–SCR–10/05
AT83C26
DC/DC converters
DC/DC A converter
The DC/DC A converter is controlled by VCARD1[1:0], SHUTDOWNA, ICCADJA, STEPREGA,
VCARD_OK1 and DEMBOOSTA[1:0] bits.
The DC/DC A converter cannot be switched on while the CPRES1 pin remains inactive. If
CPRES1 pin becomes inactive while the DC/DC A converter is operating an automatic shut
down sequence of the DC/DC A converter is initiated by the electronics.
A write operation in VCARD1[1:0] (0x01, 0x02, 0x03) starts the DC/DC. When the output voltage
remains within the voltage range specified by VCARD1[1:0], the VCARD_OK1 bit is set.
After a deactivation sequence (card extraction, DC/DC output voltage out of range, SHUT-
DOWNA bit =1...) the DC/DC A converter is automatically stopped.
It is mandatory to switch off the DC/DC A converter before entering in Power-down mode.
The DC/DC A Converter can work in two different modes which are selected by STEPREGA bit:
• Pump Mode (STEPREGA = 0): an external inductance of 10 µH must be connected
between pins LIA and VCC. VCC can be higher or lower than CVCC1.
• Regulator mode (STEPREGA = 1): no external inductance is required but VCC must be
always higher than CVCC+0.3V.
The current drawn from power supply by the DC/DC A converter is controlled during the startup
phase in order to avoid high transient current mainly in Pump Mode which could cause the
power supply voltage to drop dramatically. This control is done by means of bits DEM-
BOOSTA[1:0], which increases progressively the startup current level.
The DC/DCA sensitivity to any overflow current can be modified (20%) by using the ICCADJA bit
(SC1_CFG3 register).
Initialization Procedure for DC/DC A converter
The initialization procedure is described in flow chart:
• Select the CVCC1 level by means of bits VCARD1[1:0] in SC1_CFG0 register,
• Set bits DEMBOOSTA[1:0] in SC1_CFG4 register following the current level control wanted.
• Monitor VCARD_OK1 bit in SC1_STATUS register in order to know when the DC/DC A
Converter is ready (CVCC1 voltage has reached the expected level)
While VCC1 remains higher than 3.6V and startup current lower than 30 mA (depending on the
load type), the DC/DC A converter should be ready without having to increment DEM-
BOOSTA[1:0] bits beyond [0:0] level. If at least one of the two conditions are not met (VCC <
3.6V or startup current > 30 mA), it will be necessary to increment the DEMBOOSTA[1:0] bits
until the DC/DC converter is ready.
Increment of DEMBOOSTA[1:0] bits increases at the same time the current overflow level in the
same proportion as the startup current. So once the DC/DC converter is ready it advised to dec-
rement the DEMBOOSTA[1:0] bits to restore the overflow current to its normal or desired value.