Rainbow Electronics AT83C26 - Manual (Page 14)

14
7511B–SCR–10/05
AT83C26
Figure 4. Clock Block Diagram with Software Activation
CRST controller
CRSTn for SCn interface (n=1, 2)
The CRSTn output pin is driven by the CARDRSTn bit value or by A1/RST pin.
Three modes are available:
• If the ARTn bit is reset, CRSTn pin is driven by CARDRSTn bit.
• If the ARTn bit is set, CRSTn pin is controlled and follows the “Automatic Reset Transition”
(see Activation sequence page 25).
• A transparent mode with A1/RST pin.
Figure 5. CRSTn Block Diagram
DCK[2:0]
CKSn[2:0]
CLK
A2/CK
CCLKn
DC/DCA
0
1
CKSTOPn bit
CARDCKn bit
Internal
oscillators
and B
DCCLK
CRSTn
0
1
ARTn bit
CARDRSTn bit
CARDRSTn bit tb delay
A1/RST
0
1
CRST_SELn bit