Teledyne LeCroy
Contents
6
Kibra DDR Protocol Analyzer User Manual
3.9 Row Usage Report............................................................................................................. 146
Defining Target Row(s)..................................................................................................................... 147
Define Analysis Detail Parameters .................................................................................................. 148
Define Report Boundary................................................................................................................... 149
Cyclic Row Usage Report................................................................................................................. 149
3.10 Timing Violation Reanalysis ............................................................................................ 149
Chapter 4: Real Time Statistics .........................................................................151
4.1 Devices Dashboard ............................................................................................................ 151
4.2 Real-Time Statistics View .................................................................................................. 152
4.2.1 Command Statistics .................................................................................................................................154
4.2.2 Last MRS Values .......................................................................................................................................154
4.2.3 Real-Time Statistics Buttons ...................................................................................................................154
4.2.4 RTS Preferences .......................................................................................................................................156
4.2.5 RTS Print....................................................................................................................................................157
Appendix A: Application Note ...........................................................................159
5.1 DDR3 and DDR4 JEDEC Timing Violations Summary .................................................... 159
5.1.1 V01 - tRAS ACTIVATE to PRECHARGE command period (Min)...........................................................159
5.1.2 V02 - tRAS ACTIVATE to PRECHARGE command period (Max) ..........................................................159
5.1.3 V03 - tRRD ACTIVATE to ACTIVATE command period (DDR3 different bank, same rank) (DDR4 - same bank group).......160
5.1.4 V04 - tFAW Four Activate Window ..........................................................................................................160
5.1.5 V05 - tRCDx ACTIVATE to internal read or write delay (same bank) ...................................................160
5.1.6 V06 - tWTP WRITE to PRECHARGE delay ..............................................................................................161
5.1.7 V07 - tRTPx READ to PRECHARGE delay ..............................................................................................161
5.1.8 V08 - tRP PRECHARGE to a Valid Command.........................................................................................161
5.1.9 V09 - tWRA WRA to a Valid Command....................................................................................................161
5.1.10 V10 - t RFC REFRESH to a Valid Command .........................................................................................162
5.1.11 V11 - tREFI REFRESH Interval ...............................................................................................................162
5.1.12 V12 - tRTR READ to READ delay (DDR3 - same rank) (DDR4 - same bank group)...........................162
5.1.13 V13 - tdrRTR READ to READ delay (different rank - same DIMM) ......................................................162
5.1.14 V14 - tddRTR READ to READ delay (different DIMM) ..........................................................................162
5.1.15 V15 - tRTW READ to WRITE delay (same rank)....................................................................................163
5.1.16 V16 - tdrRTW READ to WRITE delay (different rank, same DIMM) .....................................................163
5.1.17 V17 - tddRTW READ to WRITE delay (different DIMM) ........................................................................163
5.1.18 V18 - tWTR WRITE to READ delay ( DDR3 - same rank) (DDR4 - same bank group) .......................163
5.1.19 V19 - tdrWTR WRITE to READ delay (different rank, same DIMM) .....................................................163
5.1.20 V20 - tddWTR WRITE to READ delay (different DIMM) ........................................................................163
5.1.21 V21 - tWTW WRITE to WRITE delay ( DDR3 - same rank) (DDR4 - same bank group) .....................163
5.1.22 V22 - tddWTW WRITE to WRITE delay (different rank, same DIMM) ..................................................164
5.1.23 V23 - tddWTW WRITE to WRITE delay (different DIMM)......................................................................164
