Atmel ATA6264 - Manual (Page 26)

26
4929B–AUTO–01/07
ATA6264 [Preliminary]
Figure 9-3. Functional Principle of the EVZ Regulator
The output transistor conduction is suppressed immediately if the current through the power
FET exceeds a certain level, determined by the voltage drop across an external resistor in the
range of 0.2
Ω
. The ATA6264 itself will see a voltage at the OCEVZ pin. If this voltage exceeds
typically 0.5V, the output transistor conduction has to be suppressed.
The external FET also has to be switched off if a low battery voltage at K30 or overvoltage on pin
EVZ is detected. Multiple output pulses at pin GEVZ during one oscillator period are suppressed
by internal logic.
In the default state - for example, before the minimum input voltage for starting the regulator has
been reached - the external transistor is switched off.
During startup, the voltage on pin EVZ is too low and the PWM comparator requires a duty cycle
of more than 90%. Due to an increasing inductance current, after several periods the overcur-
rent sensor becomes active and reduces the maximum duty cycle to improve magnetic energy
transfer.
Figure 9-4. Output Current During Start-up
A capacitance of 10 mF or more may be applied at pin EVZ. The equivalent series resistance
(ESR) should have a value of less than 0.5
Ω
.
After power-on, the default state of the internal dividers should always be the low EVZ voltage
divider.
The voltage at pin GNDA is compared with the voltage at pin GNDD, and if GNDA is not con-
nected, bit b6 of the APACE status register is set. Pin GNDB is also compared with pin GNDD.
Pin GNDB not being connected will also result in bit b6 being set, and, additionally, in the EVZ
regulator being switched off.
t
t
Error amp. output = f (V
EVZ
)
Sawtooth
PWM
output
off
on
Output
current
Current limit
t