Atmel ATA6264 - Manual (Page 43)

43
4929B–AUTO–01/07
ATA6264 [Preliminary]
The RESQ2 signal results from a logical AND of the Reset signal and an OK signal from the
watchdog circuitry, so RESQ2 will go high after the watchdog triggers correctly.
RESQ and RESQ2 have to be set to low if V
VPERI
or V
EVZ
are below the specified threshold.
VCORE is designed as an essential supply for a microcontroller core, and therefore special
supervisor circuits for this regulator will affect the signals at pin RESQ and RESQ2 such that
both outputs are set to low if the voltage at pin VCORE spends more than 4 regulator cycles in
an overvoltage or undervoltage condition at their corresponding switching marks. In addition, a
detected overcurrent signal during switch-on gives information about regulator problems, and
results in a low-level signal for RESQ/RESQ2.
Figure 15-3. Functional Principle of the Supervisor Circuit for VCORE Monitoring (Values are
Valid for V
VCORE
= 1.88V and V
VPERI
= 3.3V)
If the watchdog is triggered incorrectly, RESQ and RESQ2 are set to low as well. Voltage spikes
on EVZ smaller than or equal to 10 µs to 20 µs do not influence the RESQ or RESQ2 pins.
If the ATA6264 internal supply voltage (VINT) is below its proper value, RESQ and RESQ2 are
also set to low.
For all voltages at VPERI below the reset threshold, pins RESQ and RESQ2 are switched to
low. Both pins deliver a valid low until VPERI goes lower than 1V.
CLK
Q D
CLK
Q D
-
+
3.0V to 3.16V
-
+
HIGH: 7.5V to 9V
LOW: 5.5V to 6V
CLK
Q D
CLK
Q D +
-
1.68V to 1.73V
Regulator OFF
VCORE
Voltage
Signal overcurrent VCORE at
regulator ON
ON ON
ON OFF OFF
Regulator ON
RESQ
+
-
3.44V to 3.6V
VPERI
VCORE
EVZ
CLK
Q D
CLK
Q D
CLK
Q D
CLK
Q D -
+
2.03V to 2.08V