Atmel ATA6264 - Manual (Page 68)

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4929B–AUTO–01/07
ATA6264 [Preliminary]
22. Serial Interface Commands
22.1 Overview
All functions of the ATA6264 are triggered by 16-bit serial interface commands. Some of these
commands are latched because their actions have to continue for a longer time. Other com-
mands have to be executed as long as no other command is received via the serial interface.
The pin SSQ (low active) is used to select the ATA6264. If pin SSQ is inactive (high), the output
pin MISO is disabled (tristate) and the signals at the pins SCLK and MOSI are ignored and do
not affect the data in the serial interface register.
With the falling edge at pin SSQ, the ATA6264 response on the previous command is latched in
the ATA6264 status register and, after a short delay time, the signal at pin MISO is valid. With
the rising edge at pin SCLK, the data at pin MOSI is shifted into the serial interface input register
and the next bit of the status register is shifted to pin MISO. A command received at pin MOSI is
valid and will be executed if the number of rising edges at pin SCLK was exactly 16 during data
transmission; otherwise, the received signal will be ignored.
The slave select pin, SSQ, allows the individual selection of different slave SPI devices. Slave
devices that are not selected do not interfere with SPI bus activities. To ensure deactivation of
the device in case of an open SSQ pin, an internal current source is implemented to drive the
SSQ pin to high level (VPERI).
All commands, independent of their function, consist of 16 bits. The serial interface includes a
16-bit input shift register, 16-bit latches, and a decoder logic block for the generation of the SPI
command signals.
To suppress data transfer errors in the case of spikes or glitches on the clock signal, a
16-clock-cycle counter is provided. Only after 16 clock cycles does the rising edge of SSQ cause
an internal signal latch enable, which transfers the data from the shift register to the 16-bit latch.
The data word is decoded to address the correct functional block.
Table 22-1. Electrical Characteristics – Serial Interface Commands
No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*
21.1
SSQ to SCLK rising-edge
isolation
SCLK t
iso
100 ns A (3)
21.2 SSQ lag time SSQ t
lag
100 ns A (3)
21.3 Fall time
SSQ, SCLK,
MOSI
t
f
20 ns A (3)
21.3a Fall time (2) MISO t
f
20 ns A
21.4 Rise time
SSQ, SCLK,
MOSI
t
r
20 ns A (3)
21.4a Rise time (2) MISO t
r
20 ns A
21.5 Data set-up time MOSI t
su
20 ns A (3)
21.6 Data hold time MOSI t
hold
20 ns A (3)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Voltage levels for serial interface timing measurements: High level = 0.7
×
V
VPERI
, low level = 0.2
×
V
VPERI
2. Timing specified with a 100-pF external load at pin MISO
3. System requirement