Atmel ATA6264 - Manual (Page 49)

49
4929B–AUTO–01/07
ATA6264 [Preliminary]
The trigger watchdog cycle can be set to the following retrigger times:
• 4 ms
• 8 ms
• 16 ms (default)
• 32 ms
• 64 ms
• 128 ms
Cyclic phase:
Between two trigger commands a different SPI command must be seen by the SPI decoder
Figure 16-3. Watchdog Trigger Functional Principle (Successful Watchdog Trigger)
Serial
interface
communication
chip
internal
trigger
window
t_retrigger t_retrigger
t_retrigger
RESQ
t
t
t
inactive
Additional SPI-CMD
T
rg Wdg
CMD
T
rg Wdg
CMD
Additional SPI-CMD
T
rg Wdg
CMD
Additional SPI-CMD
T
rg Wdg
CMD
4 4 4 4