AOC P/N : 41A50-144 - Manual (Page 59)

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2.6.3 Panel Interface Drive Strength
As mentioned previously, the gmZAN1 has programmable output pads for the TFT panel interface. Three groups of
panel interface pads (panel clock, data, and control) are independently controllable and are programmed using API
calls. See the API reference manual for details.
Table 14. Panel Interface Pad Drive Strength
Value (4 bits) Drive Strength in mA
0 Outputs are in tri-state condition
1 2mA
2 4mA
3 6mA
4 8mA
5 10mA
6 12mA
7 14mA
8 16mA
9 18mA
10,11,12,13,14,15 20mA
2.7 Host Interface
The host microcontroller interface of the gmZAN1 has two modes of operation: gmB120 compatible mode, and a 4-
bit serial interface mode.
z
GmB120 compatible mode-Four signals consisting of 1 data bit, a frame synchronization signal, a clock signal
and an Interrupt Request signal (IRQ). This mode is entered when a pull-down resistor is not connected to
MFB6(pin number 106).
z 4-bit serial interface mode-Same as gmB120 compatible mode with the addition of three data bits so that four
data bits are transferred on each clock edge. This mode is entered when a (10K ohm) pull-down resistor is
connected to MFB6(pin number 106).
When the chip is configured for 4-bit host interface, MFB9:7 are used as HDATA3:1 and HDATA is used as
HDATA0. For instruction, Read Data, or Write Data, the data order is D3:0, D7:4, D11:8, The burst mode operation
then uses three clocks (instead of twelve) for each 12-bit data (or address) transmission.
In both modes, a reset pin sets the chip to a known state when the pin is pulled low. The RESETn pin must be low for
at least 100ns after the CVDD has become stable (between +3.15V and +3.45V) in order to reset the chip to a known
state.
The gmZAN1 chip has an on-chip pull-down resistor in the HFS input pad. No external pull-up is required. The signal
stays low until driven high by the microcontroller.