Kontron VSBC-32 - Manual (Page 37)

VSBC-32 Functional Description
ID 21168, Rev. 04 Page 2 - 5 © PEP Modular Computers GmbH
2.2.2 Memory Configurations
The VSBC-32(E) allows a significant variety of memory configurations. The special
DRAM/flash piggybacks (DM60x), for instance, allows the user to take advantage of the
on-board programming facility to produce low cost upgrades by simply overwriting exist-
ing stored data. This memory can be configured with different memory options allowing
remarkable flexibility when customizing memory requirements for real-time applications.
The DM60x piggybacks provide between 1MB and 64MB of DRAM with 32-bit access
and up to 4MB of +5V flash memory. In addition, a set of DIP sockets located on the
VSBC-32(E) mainboard allows the installation of an additional 1MB of flash/EPROM.
Both memory devices can be used for bootstrapping. The selection of the boot memory
is achieved by hardware jumpering.
Exchange and retention of system relevant data from the VMEbus to the CPU/DMA and
viceversa is provided by means of 256kB or 1MB of a 16-bit wide dual-ported SRAM
which is backed-up using Gold Caps. Both the VMEbus users and the on-board CPU
have access to the SRAM memory.
Configuration data are stored in a 2kbit EEPROM. 1kbit is used for factory-specific con-
figuration purposes, and 1kbit is available for application-specific configuration data.
Table 2-2: External Autovector and Mailbox Interrupts
Source Interrupt Source Interrupt Type
ABORT / ACFAIL MC68(EN)360, pin IRQ7 Autovector 7
Reserved MC68(EN)360, pin IRQ6 Autovector 6
Mailbox IRQ MC68(EN)360, pin IRQ5 Autovector 5
Reserved MC68(EN)360, pin IRQ4 Autovector 4
SYSFAIL MC68(EN)360, pin IRQ3 Autovector 3
Reserved MC68(EN)360, pin IRQ2 Autovector 2
Reserved MC68(EN)360, pin IRQ1 Autovector 1
Mailbox Pending Bit P_IRQ5 Control/status register
Note...
Physically the DM60x piggybacks provide up to 64MB of DRAM.
However, the IUC-32(E) mainboard envisages addressing for up to
two memory banks of 64MB each.
Note...
The upper 8kB of dual-ported SRAM are accessed by the
VMEbus, the lower 8kB are reserved for mailbox interrupts.