Kontron VSBC-32 - Manual (Page 66)

VSBC-32 Configuration
ID 21168, Rev. 04 Page 4 - 6 © PEP Modular Computers GmbH
4.2.2 Board Control/Status Register
Figure 4-2: CS7 + 0x7 Bitmap
Address: CS7 + 0x7
Format: Byte
Access: Read/write
Value after HW Reset: 0
PEP Default Address: 0x 0D 00 00 07
Table 4-6: Register Description
Name
Register
Value
Access Description
WDG
bit 7
Read/Write
Set by watchdog timer when timout has been reached. Used to
differentiate between resets caused by the watchdog and
resets caused by the reset button (power up resets can be
identified within the MC68(EN)360).
BERR2
bit 6
Read/Write
Set by VMEbus error timer on timeout to identify bus errors
caused by this timer.
(See also VMEbus status/control register)
BERR1
bit 5
Read/Write
Set by on-board bus error timer on timeout to identify bus
errors caused by this timer.
EN_WDG
bit 4
1 Read/Write
Enables the watchdog timer. It can only be set once, and
remains enabled until the next reset.
TR_WDG
bit 3
1 Read/Write Triggers the watchdog timer. Watchdog timeout = 512ms.
EN_BERR1
bit 2
1 Read/Write
Enables the on-board bus error timer. It also monitors all
on-board I/O cycles, including the time from the VMEbus
request to the VMEbus grant. Timeout = 8µ s.
ACFAIL
bit 1
1 Read/Write
VME ACFAIL signal latched when active in order to distinguish
a level 7 NMI from an ABORT or ACFAIL.
LED_G
bit 0
1 Read/Write Enables the green ‘general purpose’ front panel LED.
Warning!
The correct functionality of your equipment may be jeopardized
due to a loss of information, if bit 7 is written to. Therefore, the
customer should not write any data to bit 7.
EN_BERR1 TR_WDG ACFAIL LED_G
0 1 2 3 4 5 6 7
WDG EN_WDG BERR1 BERR2