Kontron VSBC-32 - Manual (Page 97)

VSBC-32 CXC
ID 21168, Rev. 04 Page C - 7 © PEP Modular Computers GmbH
C.4 Timing
Figure C-1: (E)CXC Signal Timing
Legend:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11. Address valid to_AS, _DS
_AS asserted
_AS negated to R/_W invalid
Data-in valid to _EDTACK
_CXC-CSx asserted to AS valid
_EDTACK negated to AS negated
Data-in hold time
_AS negated
_AS, R/_W asserted to _DS asserted
Data-out valid to _DS asserted
_AS, _DS negated to data-out invalid
Min.
10ns
80ns
10ns
0ns
-
0ns
0ns
50ns
20ns
15ns
0ns
Max.
-
-
-
-
25ns
90ns
50ns
-
-
-
-
A1-A7:
_AS:
_LDS/_UDS:
R/_W:
_EDTACK:
_CXC-CSx:
Recommended:
address lines
address strobe
lower/upper data strobe
read not write
external data transfer acknowledge
_CXC-CS0 to _CXC-CS7
Assert _EDTACK with CSx and _UDS/_LDS and “data valid“ during read cycles
Latch data with CSx and _UDS/_LDS during write cycles
Negate _EDTACK with _UDS/_LDS invalid