Kontron VSBC-32 - Manual (Page 46)

VSBC-32 Functional Description
ID 21168, Rev. 04 Page 2 - 14 © PEP Modular Computers GmbH
The VSBC-32(E) also provides a bus monitor for the VMEbus. A 128µs bus error timer
monitors the cycle lengths of the VMEbus data transfer and generates a VMEbus BERR*
signal on timeout. This timer is enabled and disabled via the VMEbus control/status reg-
ister which contains alsao a timeout status bit in order to identify the bus errors generated
by the bus monitor.
Exchange and retention of system relevant data from the VMEbus to the CPU/DMA and
viceversa is provided by means of 256kB or 1MB of a 16-bit wide dual-ported SRAM
which is backed-up using Gold Caps. Both the VMEbus users and the on-board CPU
have access to the SRAM memory (upper 8kB, i.e. even Byte addresses).
An external VMEbus master may interrupt the VSBC-32(E) by setting P_IRQ5 (“mailbox
interrupt pending”) in the VMEbus control/status register. Seen from the VMEbus, the
address of this dual-ported register is identical to the base address of the dual-ported
SRAM (lower 8kB, i.e. odd Byte addresses).
For a complete map of the VMEbus control/status register please refer to the relating
section in the Configuration chapter of this manual.
For any general VMEbus information including generic pinouts please refer to Appendix
B of the ANSI/VITA VME64 Specification.
2.4.7 CXC Mezzanine Interface
The VSBC-32(E) is equipped with a CXC mezzanine interface connector.
CXC and eCXC both contain a 16-bit data bus, seven address lines and eight decoded
chip select lines. In total, there are eight control signals (CXC_CS0...CXC_CS7). The
base address of the CXC can be programmed via the CS5 line of the MC68(EN)360.
The main difference between the two VITA standards is the amount of address space
available for peripheral devices:
• CXC: 8*256Bytes (overall length: 0x400H, 1024Bytes actually available)
• eCXC: 8*16MB (overall length: 0x1000 000, 16MB actually available)
Furthermore, the (e)CXC contains a 4-IRQ capability (4 edge-sensitive interrupt
requests), DMA capability (1 channel, DREQ + DACK), serial ports (3 channels, Full
MODEM) and a set of parallel port signals. These special CXC functions are based on
the MC68(EN)360 controller resources.
Note...
The dual-ported SRAM cannot be accessed through its own
VMEbus interface. A bus monitor timeout would result due to the
fact that any access by the VMEbus to the DPRAM would be
blocked as long as the VSBC-32(E) is bus master.
Note...
All bits of the VMEbus control/status register can be read from
the VMEbus, but only the bit P_IRQ5 is read/write.