Kontron AM4211 - Manual (Page 79)

C-4 AM4211
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IPMB-A Intelligent Platform Management Bus A
IPMB-B Intelligent Platform Management Bus B
IPMB-L Intelligent Platform Management Bus Local
IPMC Intelligent Platform Management Controller
IPMI Intelligent Platform Management Interface
IPMIFWU Intelligent Platform Management Interface FirmWare Update
IPv6 Internet Protocol version 6
IRQ Interrupt ReQuest
ISA Industry Standard Architecture. 16-bit (XT) bus architecture.
ISE Xilinx electronic design automation (EDA) tools for use with its devices.
ISO International Organization for Standardization
ITU International Telecommunication Union
ITU-T ITU Telecommunication standardization sector. ITU is International Telecommunication Union.
JTAG Joint Test Action Group
KB KiloByte
KHz KiloHertz
LAN Local Area Network
LBA Logical Block Addressing
LBC Local Bus Controller (On PowerQuicc III CPU)
LED Light-Emitting Diode
LFM Low Frequency Mode. The lowest operating speed for the processor.
LIP
Loop Initialization Primitive. Related to FC arbitrated loop topology (an initial message needed for
learning the loop addresses and acquiring one).
LSB Least Significant Byte
LUN Logical Unit Number
LV Low Voltage
LVCMOS Low-Voltage Complementary Metal Oxide Semiconductor
LVDS Low-Voltage Differential Signaling
MAC Media Access Controller address of a computer networking device.
MB MegaByte
MC Management Controller
MCH Memory Controller Hub
MemBIST
(same as MBIST). Memory Built-In Selft-Test. Chipset feature for out-of-band memory testing and
intialization.
MDn Message Digest algorithm (n=2, 5)
MDI Medium Dependent Interface. MDI port or uplink port.
MHz MegaHertz
MMC Module Management Controller. MMCs are linked to the IPMC.
MMIO Memory-Mapped IO
MP MultiProcessor
MPS MultiProcessor Specification
MRC
Memory Reference Code. Chipset specific code provided by the manufacturer and integrated into the
BIOS to test and intialize the system memory.
Acronyms Descriptions