Compaq 21264 - Manual (Page 281)

Alpha 21264/EV67 Hardware Reference Manual Alpha Instruction Set A–15
IEEE Floating-Point Conformance
The 21264/EV67 does not produce a denormal result for the underflow exception.
Instead, a true zero (+0) is written to the destination register. In the 21264/EV67,
the FPCR underflow to zero (UNDZ) bit must be set if the underflow disable
(UNFD) bit is set. If desired, trapping on underflow can be enabled by the instruc-
tion and the FPCR, and software may compute the denormal value as defined in the
IEEE standard.
The 21264/EV67 records floating-point exception information in two places:
• The FPCR status bits record the occurrence of all exceptions that are detected,
whether or not the corresponding trap is enabled. The status bits are cleared only
through an explicit clear command (MT_FPCR); hence, the exception information
they record is a summary of all exceptions that have occurred since the last time
they were cleared.
• If an exception is detected and the corresponding trap is enabled by the instruction,
and is not disabled by the FPCR control bits, the 21264/EV67 will record the
condition in the EXC_SUM register and initiate an arithmetic trap.
The following items apply to Table A–11:
• The 21264/EV67 traps on a denormal input operand for all arithmetic operations
unless FPCR[DNZ] = 1.
• Input operand traps take precedence over arithmetic result traps.
• The following abbreviations are used:
Inf: Infinity
QNaN: Quiet NaN
SNaN: Signalling NaN
CQNaN: Canonical Quiet NaN
For IEEE instructions with /S, Table A–11 lists all exceptional input and output
conditions recognized by the 21264/EV67, along with the result and exception gen-
erated for each condition.
Table A–11 Exceptional Input and Output Conditions
Alpha Instructions
21264/EV67 Hardware
Supplied Result
Exception
ADDx SUBx INPUT
Inf operand ±Inf (none)
QNaN operand QNaN (none)
SNaN operand QNaN Invalid Op
Effective subtract of two Inf operands CQNaN Invalid Op
ADDx SUBx OUTPUT
Exponent overflow ±Inf or ±MAX Overflow
Exponent underflow +0 Underflow
Inexact result Result Inexact