Alpha 21264/EV67 Hardware Reference Manual
ix
11.5.2
SROM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11–5
11.5.2.1
Serial Instruction Cache Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11–6
11.6
Notes on IEEE 1149.1 Operation and Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11–7
A
Alpha Instruction Set
A.1
Alpha Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1
A.2
Reserved Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8
A.2.1
Opcodes Reserved for Compaq. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8
A.2.2
Opcodes Reserved for PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–9
A.3
IEEE Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–9
A.4
VAX Floating-Point Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–11
A.5
Independent Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–11
A.6
Opcode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–12
A.7
Required PALcode Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–13
A.8
IEEE Floating-Point Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–14
B
21264/EV67 Boundary-Scan Register
B.1
Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
B.1.1
BSDL Description of the Alpha 21264/EV67 Boundary-Scan Register . . . . . . . . . . . . .
B–1
C
Serial Icache Load Predecode Values
D
PALcode Restrictions and Guidelines
D.1
Restriction 1 : Reset Sequence Required by Retire Logic and Mapper . . . . . . . . . . . . . . .
D–1
D.2
Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group . . . . . . . . . . . . . . .
D–8
D.3
Restriction 4 : No Writers and Readers to IPRs in Same Scoreboard Group . . . . . . . . . .
D–8
D.4
Guideline 6 : Avoid Consecutive Read-Modify-Write-Read-Modify-Write . . . . . . . . . . . .
D–9
D.5
Restriction 7 : Replay Trap, Interrupt Code Sequence, and STF/ITOF . . . . . . . . . . . . . . .
D–9
D.6
Restriction 9 : PALmode Istream Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–10
D.7
Restriction 10: Duplicate IPR Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–10
D.8
Restriction 11: Ibox IPR Update Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–11
D.9
Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM
D–11
D.10
Restriction 13 : DTB Fill Flow Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–11
D.11
Restriction 14 : HW_RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–11
D.12
Guideline 16 : JSR-BAD VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12
D.13
Restriction 17: MTPR to DTB_TAG0/DTB_PTE0/DTB_TAG1/DTB_PTE1 . . . . . . . . . . . . .
D–12
D.14
Restriction 18: No FP Operates, FP Conditional Branches, FTOI, or STF in Same Fetch Block as
HW_MTPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–12
D.15
Restriction 19: HW_RET/STALL After Updating the FPCR by way of MT_FPCR in PALmode D–12
D.16
Guideline 20 : I_CTL[SBE] Stream Buffer Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–12
D.17
Restriction 21: HW_RET/STALL After HW_MTPR ASN0/ASN1. . . . . . . . . . . . . . . . . . . . . .
D–12
D.18
Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1. . . . . . . . . . . . . . . . . . . . . . . . . .
D–13
D.19
Restriction 23: HW_ST/P/CONDITIONAL Does Not Clear the Lock Flag. . . . . . . . . . . . . . .
D–13
D.20
Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP
D–
14
D.21
Restriction 25: HW_MTPR ITB_IA After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–14
D.22
Guideline 26: Conditional Branches in PALcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–14
D.23
Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PALcode . . . . . . . . . . . . . . . . . . . . .
D–15
D.24
Restriction 28: Enforce Ordering Between IPRs Implicitly Written by Loads and Subsequent Loads
D–15
D.25
Guideline 29 : JSR, JMP, RET, and JSR_COR in PALcode . . . . . . . . . . . . . . . . . . . . . . . . .
D–15