Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement - Manual (Page 32)

MAXQ Family User’s Guide:
MAXQ8913 Supplement
5-4
Table 5-3. Peripheral Register Bit Reset Values (continued)
Note: Bits marked as “s” have special behavior upon reset; see the register descriptions for details.
REG
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPIB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2CCN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2CST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2CBUF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2CIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SMD 0 0 0 0 0 0 0 0
PR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPICF 0 0 0 0 0 0 0 0
SPICK 0 0 0 0 0 0 0 0
I2CCK 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
I2CTO 0 0 0 0 0 0 0 0
I2CSLA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCNT 0 0 0 0 0 0 0 0
MA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TBCN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TBR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MC1R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MC0R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TBV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TBC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DAC1OUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DAC2OUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DAC3OUT 0 0 0 0 0 0 0 0
DAC4OUT 0 0 0 0 0 0 0 0
AMPCN 0 1 0 0 0 0 0 0
ISINKCN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADDATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPMCN 0 0 0 0 0 0 0 0
DACEN 0 0 0 0 0 0 0 0
TEMPEN 0 0 0 0 0 0 0 0
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