Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement - Manual (Page 91)

MAXQ Family User’s Guide:
MAXQ8913 Supplement
22-5
Bit 8: I 2 C General Call Enable (I2CGCEN). Setting this bit to 1 enables the I 2 C to respond to a general call address
(address = 0000 0000). Clearing this bit to 0 prevents the I 2 C from responding to the general call address.
Bit 7: I 2 C STOP Enable (I2CSTOP). Setting this bit to 1 generates a STOP condition. This bit automatically is self-
cleared to 0 after the STOP condition has been generated.
In master mode, setting this bit can also start the timeout timer if enabled. If the timeout timer expires before the STOP
condition can be generated, a timeout interrupt is generated to the CPU if enabled. The I2CSTOP bit is also cleared
to 0 by the timeout event.
Note that this bit has no effect when the I
2 C is operating in slave mode (I2CMST = 0), and is reset to 0 when I2CMST
= 0 or I2CEN = 0. Setting the I2CSTOP bit to 1 while I2CSTART = 1 is an invalid operation and is ignored, leaving
I2CSTOP bit cleared to 0.
Bit 6: I
2 C START (I2CSTART). Setting this bit automatically generates a START condition when the bus is free or
generates a repeated START condition during a transfer where the I 2 C module is operating as the master. This bit is
automatically self-cleared to 0 after the START condition has been generated. If the I 2 C START interrupt is enabled, a
START condition generates an interrupt to the CPU.
In master mode, setting this bit can also start the timeout timer if enabled. If the timeout timer expires before the START
condition can be generated, a timeout interrupt is generated to the CPU if enabled. The I2CSTART bit is also cleared
to 0 by the timeout event.
Note that this bit has no effect when the I
2 C is operating in slave mode (I2CMST = 0) and is reset to 0 when I2CMST
= 0 or I2CEN = 0. Also, the I2CSTART and I2CSTOP bits are mutually exclusive. If both bits are set at the same time,
it is considered as an invalid operation and the I
2 C controller ignores the request and resets both bits to 0. Setting the
I2CSTART bit to 1 while I2CSTOP = 1 is an invalid operation and is ignored, leaving the I2CSTART bit cleared to 0.
Bit 5: I
2 C Data Acknowledge Bit (I2CACK). This bit selects the acknowledge bit returned by the I 2 C controller while
acting as a receiver. Setting this bit to 1 generates a NACK (leaving SDA high). Clearing the I2CACK bit to 0 generates
an ACK (pulling SDA low) during the acknowledgement cycle. This bit retains its value unless changed by software or
hardware. When an I
2 C abort is in progress (I2CRST = 1), this bit is set to 1 by hardware, and software writes to this
bit are ignored when I2CRST = 1.
Bit 4: I
2 C Clock Stretch Select (I2CSTRS). Setting this bit to 1 enables clock stretching after the falling edge of the
8th clock cycle. Clearing this bit to 0 enables clock stretching after the falling edge of the 9th clock cycle. This bit has
no effect when clock stretching is disabled (I2CSTREN = 0).
Bit 3: I
2 C Extended Address Mode Enable (I2CEA). When this bit is set to 0 (the default), all address transmissions in
master mode operate using a 7-bit address, and the slave mode functions match against a 7-bit address. Setting this
bit to 1 increases the address range to 10 bits for both master mode transmissions and slave mode address matches.
Bit 2: I
2 C Transfer Mode (I2CMODE). The transfer mode bit selects the direction of data transfer with respect to the
master. When the I2CMODE bit is set to 1, the master is operating in receiver mode (reading from slave). When the
I2CMODE bit is cleared to 0, the master is operating in transmitter mode (writing to slave).
Note that software writing to this bit is prohibited in slave mode. When operating in master mode, software configures
this bit to the desired direction of data transfer. When operating in slave mode, the direction of data transfer is deter-
mined by the R/W bit received during the address stage, and this bit reflects the actual R/W bit value in the current
transfer and is set by hardware. Software writing to this bit in slave mode is ignored.
Bit 1: I
2 C Master-Mode Enable (I2CMST). The I2CMST bit functions as a master-mode enable bit for the I 2 C mod-
ule. When the I2CMST bit is set to 1, the I 2 C operates as a master. When the I2CMST is cleared to 0, the I 2 C module
operates in slave mode. This bit is automatically cleared whenever the I 2 C controller receives a slave address match
(I2CAMI = 1), loses arbitration (I2CALI = 1), or matches the general call address (I2CGCI = 1).
Bit 0: I
2 C Enable (I2CEN). This bit enables the I 2 C function. When set to 1, the I 2 C communication unit is enabled.
When cleared to 0, the I 2 C function is disabled.
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