Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement - Manual (Page 68)

MAXQ Family User’s Guide:
MAXQ8913 Supplement
19-6
Bits 9:8: ADC Clock Divider (ADCLK[1:0]). These bits control the generation of the ADC clock from the system clock
as follows:
However, since there is an upper limit on the sample rate of the ADC (approximately 300ksps; refer to the IC data
sheet), not all clock division settings could be valid, depending on the system clock frequency. A single ADC conver-
sion requires 16 ADC clocks, which allows us to calculate possible ADC sample rates as shown in Table 19-3.
Bit 7: ADC Internal Reference Enable (IREFEN). This bit controls the ADC internal reference.
0 = The internal reference is disabled. The ADREF bit in each configuration register (ADCFG) selects between AVDD
and the external reference.
1 = The internal reference is enabled. Once REFOK = 1, the ADREF bit in each configuration register (ADCFG) selects
between AVDD and the internal reference.
Bit 6: ADC Continuous Sequence Mode (ADCONT). This bit selects single- or continuous-sequence mode.
0 = Single-conversion sequence mode. In this mode, setting ADCONV = 1 starts a single-conversion sequence, with
starting and ending configuration registers as defined in the ADADDR register. Once the conversion sequence
completes, ADCONV automatically clears to 0, and the ADC powers down (if PMO = 0).
1 = Continuous-conversion sequence mode. In this mode, setting ADCONV = 1 also starts a conversion sequence,
but once the sequence has completed, it simply repeats again. To stop the conversions, ADCONV must explicitly
be cleared to 0 by software.
Bit 5: ADC Data Available Interrupt Enable (ADDAIE). This bit controls the ADC data available interrupt.
0 = The ADC interrupt is disabled.
1 = An interrupt is triggered (if not otherwise masked) when ADDAI = 1.
Bit 4: ADC Power-Management Override (PMO). This bit controls power management for the ADC.
0 = The ADC automatically powers up at the beginning of a conversion sequence and powers down when the
sequence has finished (or when ADCONV is set to 0). This adds a delay of approximately 20 ADC clocks to the
conversion sequence time.
1 = ADC power management is disabled. After setting PMO to 1, the software should wait long enough for the ADC to
power up before initiating a conversion (refer to the IC data sheet for timing). Once the ADC has powered up, it
remains powered on as long as PMO is set to 1, unless stop mode is entered.
Table 19-3. ADC Sample Rates Using a 10MHz Crystal
ADCLK1 ADCLK0 ADC CLOCK
0 0 System Clock/1 (default setting)
0 1 System Clock/2
1 0 System Clock/4
1 1 System Clock/8
ADCLK[1:0]
SAMPLE RATE AT
10MHz
(CLOCK/1) (ksps)
SAMPLE RATE AT
5MHz
(CLOCK/2) (ksps)
SAMPLE RATE AT
2.5MHz
(CLOCK/4) (ksps)
SAMPLE RATE AT
1.25MHz
(CLOCK/8) (ksps)
SAMPLE RATE AT
8.4MHz
(FLL) (ksps)
00
625
(invalid)
312.5 156.25 78.13
525
(invalid)
01 312.5 156.25 78.13 39
262.5
(invalid)
10 156.25 78.13 39 19.5 131
11 78.13 39 19.5 9.76 65.6
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