2 supply voltage monitor register (svm, m0[06h]), Maxq family user’s guide: maxq8913 supplement – Maxim Integrated MAXQ Family Users Guide: MAXQ8913 Supplement User Manual
Page 97
MAXQ Family User’s Guide:
MAXQ8913 Supplement
23-2
Bit 0: High-Frequency Crystal Oscillator Disable (HFXD). Setting this bit to 1 disables the high-frequency crystal
oscillator on the MAXQ8913. However, a high-frequency external clock can still be provided at HFXIN. Clearing this bit
to 0 enables the high-frequency crystal oscillator.
23.1.2 Supply Voltage Monitor Register (SVM, M0[06h])
Bits 15:12, 7:5: Reserved
Bits 11:8: Supply Voltage Monitor Threshold (SVTH[3:0]). These bits select the programmable DVDD threshold set-
ting for the SVM. The level can be adjusted from approximately 2.0V to 3.5V in steps of 0.1V, and is given by:
SVM threshold = 2.0V + (SVTH[3:0] x 0.1V)
Note: Settings below 2.7V have no effect and should not be used.
The default setting (SVTH[3:0] = 0111b) is 2.7V. Note that these bits can only be changed when SVMEN = 0.
Bit 4: Supply Voltage Monitor Stop-Mode Enable (SVMSTOP). This bit controls the operation of the SVM in stop
mode.
0 = The SVM is disabled during stop mode.
1 = The SVM is enabled during stop mode (if SVMEN = 1).
Bit 3: Supply Voltage Monitor Interrupt Flag (SVMI). This bit is set to 1 by hardware when the DVDD supply is below
the threshold voltage set by SVTH[3:0]. If SVMIE = 1, setting this bit to 1 by either hardware or software triggers an
interrupt. This bit must be cleared by software, but if DVDD is still below the threshold, the bit immediately is set by
hardware again.
Bit 2: Supply Voltage Monitor Interrupt Enable (SVMIE). Setting this bit to 1 allows an interrupt to be generated (if
not otherwise masked) when SVMI is set to 1. Clearing this bit to 0 disables the SVM interrupt.
Bit 1: Supply Voltage Monitor Ready (SVMRDY). This read-only status bit indicates whether the SVM is ready for use.
0 = The SVM is disabled (SVMEN = 0), stop mode was entered with SVMSTOP = 0, or the SVM is in the process of
warming up.
1 = The SVM is enabled and ready for use.
Bit 0: Supply Voltage Monitor Enable (SVMEN). Setting this bit to 1 enables the SVM and begins monitoring DVDD
against the programmed (SVTH[3:0]) threshold. Clearing this bit to 0 disables the SVM.
*SVTH[3:0] can only be written when the SVM is not running (SVMEN = 0).
Bit #
15
14
13
12
11
10
9
8
Name
—
—
—
—
SVTH3
SVTH2
SVTH1
SVTH0
Reset
0
0
0
0
0
1
1
1
Access
r
r
r
r
rw*
rw*
rw*
rw*
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
SVMSTOP
SVMI
SVMIE
SVMRDY
SVMEN
Reset
0
0
0
0
0
0
0
0
Access
r
r
r
rw
rw
rw
r
rw
Maxim Integrated