2 det interrupt, 3 synl interrupt, Det interrupt – Maxim Integrated 73M1822/73M1922 Implementers Guide User Manual

Page 22: Synl interrupt

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73M1822/73M1922 Implementer’s Guide

UG_1x22_052

22

Rev. 1.0

6.2 DET Interrupt

The triggering of the DET interrupt indicates that the device has detected one of several line condition
errors. When found, it can be assumed that there is a problem with the line status. The general
corrective action is for the line side device to go on hook. These interrupts are only valid when the device
is in an off hook condition.

0x05

ENGPIO7 ENGPIO6 ENGPIO5 ENGPIO4 ENAPOL

ENDET

ENSYNL ENRGDT

Write

X

X

X

X

1

1

X

X

0x12

OFH

ENDC

ENAC

ENSHL

ENLVD

ENFEL

ENDT

ENNOM

Write

1

1

1

x

x

1

1

x

0x13

DCIV1

DCIV0

ILM

RSVD

PLDM

OVDTH

IDISPD

IDISPD

Write

X

X

0

0

0

1/0

0

0

0x14

TXBST

DAA1

DAA0

Res

RXBST

RLPNH

RXG1

RXG0

Write

X

X

X

0

X

X

X

X

0x15

Res

DISNTR

Res

CIDM

THEN

ENUVD

ENOVD

ENOID

Write

0

0

0

0

1

1

1

1

0x1E

ILMON

UVDET

OVDET

OIDET

SLLS

Res

Res

Res

Read

X

?

?

?

X

X

X

X


Set the ENDET bit in Register 0x05 to enable the DET interrupt.

Begin

1. If DET = 1 (IntSrc = xxxx_x1xx).

2. Read RG1E

3. If OVDET = 1, report condition to user and put device on hook.

4. If OIDET = 1, report condition to user and put device on hook

5. If UVDET = 1, report condition to user and put device on hook

End

6.3 SYNL Interrupt

The triggering of the SYNL interrupt indicates that the device has detected a failure in the barrier between
the line and host side device. When found, it can be assumed that there is a problem with the barrier.
This failure is usually a problem with the PLL operation, therefore, the recommended way to deal with this
interrupt is to reset the device PLL.

0x05

ENGPIO7 ENGPIO6 ENGPIO5 ENGPIO4 ENAPOL

ENDET

ENSYNL ENRGDT

Write

X

X

X

X

1

X

1

X


Set the RNSYNL bit in Register 0x05 to enable the SYNL interrupt.

Begin

1. If SYNL = 1 (IntSrc = xxxx_xx1x), goto Barrier Synchronization Process (see Barrier Synchronization

Section 3.2.1)

End

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