Maxim Integrated 73M1822/73M1922 Implementers Guide - Manual (Page 5)

UG_1x22_052 73M1822/73M1922 Implementer’s Guide
Rev. 1.0 5
2 Hardware Requirements
2.1 Reset
The 73M1x22 can be initialized to a default state by pulling the
RST pin low for 100 ns or longer. The
device w
ill be ready within 100 μs after the removal of reset pulse. The M/S pin is used to provide reset in
the 73M1822 and 72M1902 20-pin TSSOP packaged parts. The reset signal is also bi-directional and
edge triggered, so either a low-to-high or high-to-low transition will generate a reset. Refer to the
73M1822/73M1922 Data Sheet for more information on the proper use of reset signals.
2.2 Crystal Oscillator
The Host-Side Device has an on-chip crystal oscillator, prescaler and PLL/NCO to allow a choice of a
wide range of sample rates and crystal choices. The crystal oscillator is designed to operate with a wide
choice of crystals (from 9 MHz to 27 MHz). It is a common source configuration with current source
loading to reduce power consumption. Refer to the 73M1822/73M1922 Data Sheet (Section 7) for
instructions on configuring the Crystal/PLL interface.
2.3 MAFE Interface
The host must use the MAFE interface for accessing all device registers. The final state of the both the
TYPE, SCKM and M/S pin will affect the operational mode of the MAFE interface the user should be
aware of their settings before attempting to program the device. Configurations such as daisy chain
modes and control frame usage will require to user to write some register settings. Refer to the
73M1822/73M1922 Data Sheet (Section 8) for instructions on configuring the MAFE interface.
2.4 Interrupts
The 73M1x22 devices provide a single hardware interrupt pin (active low – open drain) that goes active
upon detection of any of several programmable hardware events within the 73M1x22. The interrupt pin is
active and configured for operation upon reset of the 73M1x22. Because interrupts are enabled by
default, the device will generate an interrupt as soon as reset is de-asserted (due to a barrier failure
detect). The host application must be ready to service or safely ignore this interrupt before the de-
assertion of reset. The recommended way to deal with the first interrupt after reset is to disable the
interrupt generation until the system is ready to handle them (see Section 3.1.2 First Interrupt
) . Refer to
the 73M1822/73M1922 Data Sheet (Section 6.2) for instructions on configuring interrupts.