Altera RAM Initializer - Manual (Page 22)

2–10 Confidential—Internal Use Only Altera Corporation
RAM Initializer (ALTMEM_INIT) Megafunction User Guide May 2008
Design Example 1: RAM Initialization with Initialization Data File
of the Node Finder. During synthesis and place-and-route, the names of
RTL signals change. Therefore, it may be difficult to find signals from
your megafunction instantiation in the post-compilation filter.
To preserve the names of your signals during the synthesis and
place-and-route stages, use the synthesis attributes keep or preserve.
These are Verilog HDL and VHDL synthesis attributes that direct analysis
and synthesis to keep a particular wire, register, or node intact. Use these
synthesis attributes to keep a combinational logic node so you can
observe the node during simulation.
f
For more information about these attributes, refer to the Quartus II
Integrated Synthesis chapter in volume 1 of the Quartus II Handbook.
EDA Simulator
The Quartus II Handbook chapters describe how to perform functional and
gate-level timing simulations that include the megafunctions, with
details about the files that are needed and the directories where the files
are located.
f
Depending on which simulation tool you are using, refer to the
appropriate chapter in the
Simulation section in volume 3 of the
Quartus II Handbook.
Design
Example 1: RAM
Initialization
with
Initialization
Data File This design example uses the ALTMEM_INIT megafunction in the
MegaWizard Plug-In Manager to initialize the RAM of a HardCopy II
device with an initialization data file and the INIT_FILE parameter.
Design Files
To initialize the RAM, you can use the DE1_initfile.mif file, which is a
Memory Initialization File (.mif) that contains the content of the internal
ROM. You can also create your own .mif file using the Quartus II
software. The number of words and data width in the .mif file must be the
same as the corresponding parameter values in the megafunction.
Figure 2–6 shows the content of the initialization data file. In this design
example, the file has 16 words, with each word having a data width of
8 bits.