Altera RAM Initializer - Manual (Page 21)

Altera Corporation Confidential—Internal Use Only 2–9
May 2008 RAM Initializer (ALTMEM_INIT) Megafunction User Guide
Getting Started
Using the Port and Parameter Definitions
Instead of using the MegaWizard Plug-In Manager, you can instantiate
the megafunction directly in your Verilog HDL, VHDL, or AHDL code by
calling the megafunction and setting its parameters as you would any
other module, component, or subdesign.
1 Altera strongly recommends that you use the MegaWizard
Plug-In Manager for complex megafunctions. The MegaWizard
Plug-In Manager ensures that you set all megafunction
parameters properly.
For a list of the megafunction ports and parameters, refer to Chapter 3,
Specifications .
Identifying a
Megafunction
after
Compilation During compilation with the Quartus II software, analysis and
elaboration are performed to build the structure of your design. To locate
your megafunction in the Project Navigator window, expand the
compilation hierarchy and find the megafunction by its name.
To search for node names within the megafunction (using the Node
Finder), click Browse in the Look in box and select the megafunction in
the Hierarchy box.
Simulation The Quartus II Simulator provides an easy-to-use, integrated solution for
performing simulations. The following sections describe the simulation
options.
Quartus II Software Simulator
With the Quartus II Simulator, you can perform two types of simulations:
functional and timing. A functional simulation enables you to verify the
logical operation of your design without taking into consideration the
timing delays in the FPGA or HardCopy device. This simulation is
performed using only your RTL code. When performing a functional
simulation, add only signals that exist before synthesis. You can find
these signals in the Node Finder by using any of the following Filter
options: Registers: Pre-Synthesis, Design Entry, or Pins. The top-level
ports of megafunctions are found using these three filters.
In contrast, the timing simulation in the Quartus II software verifies the
operation of your design with annotated timing information. This
simulation is performed using the post place-and-route netlist. When
performing a timing simulation, add only signals that exist after
place-and-route. These signals are found with the post-compilation filter