Development board setup, Introduction, Setting up the board – Altera Arria II GX FPGA User Manual
Page 15: Chapter 4. development board setup, Introduction –1 setting up the board –1
July 2010
Altera Corporation
Arria II GX FPGA Development Kit, 6G Edition User Guide
4. Development Board Setup
Introduction
The instructions in this chapter explain how to set up the Arria II GX FPGA
development board, 6G edition.
Setting Up the Board
To prepare and apply power to the board, perform the following steps:
1. The Arria II GX FPGA development board, 6G edition ships with its board
switches preconfigured to support the design examples in the kit. If you suspect
your board might not be currently configured with the default settings, follow the
instructions in
“Factory Default Switch Settings” on page 4–2
to return the board
to its factory settings before proceeding.
2. The FPGA development board, 6G edition ships with design examples stored in
the flash memory device. Verify the USR LOAD switch (SW4.4) is set to the off
position to load the design stored in the factory portion of flash memory.
shows the switch location on the Arria II GX FPGA development
board, 6G edition.
3. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J4) on the FPGA
board and plug the cord into a power outlet.
c
Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage.
4. Set the POWER switch (SW1) to the on position. When power is supplied to the
board, a blue LED (D18) illuminates indicating that the board has power.
The MAX II device on the board contains (among other things) a parallel flash loader
(PFL) megafunction. When the board powers up, the PFL reads a design from flash
memory and configures the FPGA. The USR LOAD switch (SW4.4) controls which
design to load. When the switch is in the off position, the PFL loads the design from
the factory portion of flash memory. When the switch is in the on position, the PFL
loads the design from the user hardware 1 portion of flash memory.
1
The kit includes a MAX II design which contains the MAX II PFL megafunction. The
design resides in the <install dir>\kits\arriaIIGX_2agx260_fpga\examples\max2
directory.
When configuration is complete, the CONF DONE LED (D14) illuminates, signaling
that the Arria II GX device configured successfully.
f
For more information about the PFL megafunction, refer to
.