Altera NCO MegaCore Function User Manual
Page 14
File Name
Description
<my_ip>.cmp
The VHDL Component Declaration (.cmp) file is a text file that
contains local generic and port definitions that you can use in VHDL
design files.
<my_ip>.html
A report that contains connection information, a memory map
showing the address of each slave with respect to each master to
which it is connected, and parameter assignments.
<my_ip>_generation.rpt
IP or Qsys generation log file. A summary of the messages during IP
generation.
<my_ip>.debuginfo
Contains post-generation information. Used to pass System Console
and Bus Analyzer Toolkit information about the Qsys interconnect.
The Bus Analysis Toolkit uses this file to identify debug components
in the Qsys interconnect.
<my_ip>.qip
Contains all the required information about the IP component to
integrate and compile the IP component in the Quartus II software.
<my_ip>.csv
Contains information about the upgrade status of the IP component.
<my_ip>.bsf
A Block Symbol File (.bsf) representation of the IP variation for use
in Quartus II Block Diagram Files (.bdf).
<my_ip>.spd
Required input file for
ip-make-simscript
to generate simulation
scripts for supported simulators. The .spd file contains a list of files
generated for simulation, along with information about memories
that you can initialize.
<my_ip>.ppf
The Pin Planner File (.ppf) stores the port and node assignments for
IP components created for use with the Pin Planner.
<my_ip>_bb.v
You can use the Verilog black-box (_bb.v) file as an empty module
declaration for use as a black box.
<my_ip>.sip
Contains information required for NativeLink simulation of IP
components. You must add the .sip file to your Quartus project.
<my_ip>_inst.v
or
_inst.vhd
HDL example instantiation template. You can copy and paste the
contents of this file into your HDL file to instantiate the IP variation.
<my_ip>.regmap
If the IP contains register information, the .regmap file generates.
The .regmap file describes the register map information of master
and slave interfaces. This file complements the .sopcinfo file by
providing more detailed register information about the system. This
enables register display views and user customizable statistics in
System Console.
UG-NCO
2014.12.15
Files Generated for Altera IP Cores
2-7
NCO IP Core Getting Started
Altera Corporation