Altera NCO MegaCore Function - Manual (Page 5)

• Avalon ® Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
NCO IP Core Features
• 32-bit precision for angle and magnitude
• Source interface compatible with the Avalon Interface Specification
• Multiple NCO architectures:
• Multiplier-based implementation using DSP blocks or logic elements (LEs), (single cycle and multi-
cycle)
• Parallel or serial CORDIC-based implementation
• ROM-based implementation using embedded array blocks (EABs), embedded system blocks
(ESBs), or external ROM
• Single or dual outputs (sine/cosine)
• Variable width frequency modulation input
• Variable width phase modulation input
• User-defined frequency resolution, angular precision, and magnitude precision
• Frequency hopping
• Multichannel capability
• Simulation files and architecture-specific testbenches for VHDL, Verilog HDL and MATLAB
• Dual-output oscillator and quaternary frequency shift keying (QFSK) modulator example designs
DSP IP Core Device Family Support
Altera offers the following device support levels for Altera IP cores:
• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.
• Final support—Altera verifies the IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. You can use it in production
designs.
Table 1-1: DSP IP Core Device Family Support
Device Family Support
Arria ® II GX Final
Arria II GZ Final
Arria V Final
Arria 10 Final
Cyclone ® IV Final
Cyclone V Final
1-2 NCO IP Core Features
UG-NCO
2014.12.15
Altera Corporation About the NCO IP Core
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