Altera Partial Reconfiguration IP Core - Manual (Page 10)

Port Name Width Direction Function
status[2..0]
3
Output A 3-bit error output used to
indicate the status of PR event.
Once an error is detected (
PR_
ERROR
,
CRC_ERROR
, or Incompat‐
ible bitstream error), this signal
is latched high and only get reset
at the beginning of the next PR
event, when
pr_start
is high
and
freeze
is low. For example:
3’b000 – power-up or nreset
asserted
3’b001 – PR_ERROR was
triggered
3’b010 – CRC_ERROR was
triggered
3’b011 – Incompatible
bitstream error detected
3’b100 – PR operation in
progress
3’b101 – PR operation
passed
3'b110 – Reserved
3'b111 – Reserved
10 Partial Reconfiguration IP Core Ports
UG-PARTRECON
2015.05.04
Altera Corporation Partial Reconfiguration IP Core
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