Altera Partial Reconfiguration IP Core - Manual (Page 2)

Figure 2: Managing Partial Reconfiguration with an Internal or External Host
The figure shows how these blocks should be connected to the PR control block (CB). In your system, you
will have either the external host or the internal host, but not both. During PR, the PR Control Block (CB)
is in Passive Parallel x16 programming mode.
PR
IP Core
PR
Region
PR Bitstream
file (.rbf) in
external memory
PR Control
Block (CB)
External
Host
PR
Region
PR Bitstream
file (.rbf) in
external memory
Related Information
• FPGA Control Block Interface on page 15
• Control Block Interface Controller on page 17
• Freeze and Unfreeze Controls on page 18
• Data Source Controller on page 18
• Standard Partial Reconfiguration Data Interface on page 18
• JTAG Debug Mode for Partial Reconfiguration on page 19
Instantiating the Partial Reconfiguration IP Core in the Qsys Interface
Partial Reconfiguration(PR) is available as a Qsys component through the Qsys interface.You can choose
to instantiate the core as an internal host or an external host.
When instantiated with Qsys, PR is configured as a Conduit interface, or by enabling the Avalon
Memory Map Slave interface. If you use Qsys and want PR included as component, you must instantiate
the PR IP core in the Qsys interface.
To instantiate the PR IP core with Qsys:
1. Click Tools > Qsys
2. In the Qsys interface IP Catalog expand Basic Functions > Configuration and Programming and
select Partial Reconfiguration.
3. Configure your IP core variation using the settings appropriate to your design.
2 Instantiating the Partial Reconfiguration IP Core in the Qsys Interface
UG-PARTRECON
2015.05.04
Altera Corporation Partial Reconfiguration IP Core
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