Altera Partial Reconfiguration IP Core - Manual (Page 13)

Port Name Width Direction Function
pr_done_pin
1
Input Available when the PR IP core is
used as the External Host.
Connect this port to the
dedicated
PR_DONE
pin of the
FPGA undergoing partial
reconfiguration, or connect
directly to the
prblock
WYSIWYG atom primitive.
pr_request_pin
1
Output Available when the IP is used as
the External Host. Connect this
port to the dedicated
PR_
REQUEST
pin of the FPGA
undergoing partial reconfigura‐
tion, or connect directly to the
prblock
WYSIWYG atom
primitive.
pr_clk_pin
1
Output Available when the IP is used as
the External Host. Connect this
port to the dedicated
DCLK
of the
FPGA undergoing partial
reconfiguration, or connect
directly to the
prblock
WYSIWYG atom primitive.
pr_data_
pin[15..0]
16
Output Available when the IP is used as
the External Host. Connect this
port to the dedicated
DATA[15..0]
pins of the FPGA
undergoing partial reconfigura‐
tion, or connect directly to the
prblock
WYSIWYG atom
primitive.
Related Information
Avalon Memory Map Slave Interface Data/CSR Memory Map on page 14
Using the Avalon Memory Mapped Slave Interface
Perform partial reconfiguration through the Avalon Memory Mapped Slave interface by following these
steps:
UG-PARTRECON
2015.05.04
Using the Avalon Memory Mapped Slave Interface 13
Partial Reconfiguration IP Core Altera Corporation
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