Altera Reed-Solomon Compiler - Manual (Page 13)

Chapter 2: Getting Started 2–5
Files Generated for Altera IP Cores
December 2014 Altera Corporation Reed-Solomon Compiler
User Guide
Files Generated for Altera IP Cores
The Quartus II software version 14.0 Arria 10 Edition and later generates the
following output file structure for Altera IP cores:
Simulating IP Cores
The Quartus II software supports RTL- and gate-level design simulation of Altera IP
cores in supported EDA simulators. Simulation involves setting up your simulator
working environment, compiling simulation model libraries, and running your
simulation.
You can use the functional simulation model and the testbench or example design
generated with your IP core for simulation. The functional simulation model and
testbench files are generated in a project subdirectory. This directory may also include
scripts to compile and run the testbench. For a complete list of models or libraries
required to simulate your IP core, refer to the scripts generated with the testbench.
You can use the Quartus II NativeLink feature to automatically generate simulation
files and scripts. NativeLink launches your preferred simulator from within the
Quartus II software.
For more information about simulating Altera IP cores, refer to Simulating Altera
Designs in volume 3 of the Quartus II Handbook.
Figure 2–2. IP Core Generated Files
<Project Directory>
<your_testbench>_tb.csv
<your_testbench>_tb.spd
sim - IP core simulation files
<your_testbench>_tb - Simulation testbench files
<your_testbench>_tb
<your_ip> - IP core variation files
<your_ip>.cmp - VHDL component declaration file
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists IP synthesis files
<your_ip>.sip - Lists files for simulation
synth - IP synthesis files
<your_ip>.v or .vhd - Top-level IP synthesis file
sim - IP simulation files
1
<your_ip>.v or .vhd - Top-level simulation file
<EDA_tool_name> - Simulator setup scripts
<simulator_setup_scripts>
<IP subcore library> - IP subcore files
<HDL files>
sim
<your_ip>.qsys - System or IP integration file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>_inst.v or .vhd - Sample instantiation template
<your_ip>_generation.rpt - IP generation report
<your_ip>.debuginfo - IP generation report
<your_ip>.html - Contains memory map
<your_ip>.bsf - Block symbol schematic
<your_ip>.spd - Combines individual simulation startup scripts
1
<your_ip>_tb.qsys - Testbench system file
1
<your_ip>.sopcinfo - Software tool-chain integration file
1. If supported and enabled for your IP variation