Altera Reed-Solomon Compiler - Manual (Page 10)

2–2 Chapter 2: Getting Started
Specifying IP Core Parameters and Options
Reed-Solomon Compiler December 2014 Altera Corporation
User Guide
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation supports the following operation modes:
■ Untethered—the design runs for a limited time.
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely.
All megafunctions in a device time-out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior might be masked by the time-out behavior
of the other megafunctions.
The untethered time-out for a RS Compiler MegaCore function is one hour; the
tethered time-out value is indefinite.
Your design stops working after the hardware evaluation time expires and the data
output rsout remains low.
Specifying IP Core Parameters and Options
The parameter editor GUI allows you to quickly configure your custom IP variation.
Use the following steps to specify IP core options and parameters in the Quartus II
software. Refer to Specifying IP Core Parameters and Options (Legacy Parameter
Editors) for configuration of IP cores using the legacy parameter editor.
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP
core to customize. The parameter editor appears.
2. Specify a top-level name for your custom IP variation. The parameter editor saves
the IP variation settings in a file named .<your_ip>qsys. Click OK.
3. Specify the parameters and options for your IP variation in the parameter editor,
including one or more of the following. Refer to your IP core user guide for
information about specific IP core parameters.
■ Optionally select preset parameter values if provided for your IP core. Presets
specify initial parameter values for specific applications.
■ Specify parameters defining the IP core functionality, port configurations, and
device-specific features.
■ Specify options for processing the IP core files in other EDA tools.
4. Click Generate HDL, the Generation dialog box appears.
5. Specify output file generation options, and then click Generate. The IP variation
files generate according to your specifications.
6. To generate a simulation testbench, click Generate > Generate Testbench System.
7. To generate an HDL instantiation template that you can copy and paste into your
text editor, click Generate > HDL Example.
8. Click Finish. The parameter editor adds the top-level .qsys file to the current
project automatically. If you are prompted to manually add the .qsys file to the
project, click Project > Add/Remove Files in Project to add the file.