Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY - Manual (Page 16)

Stratix II GX Embedded Gigabit Ethernet MAC / PHY
User's Guide
Version 1.0 - October 2005
TB_CRC_FWD Boolean
Enable CRC Forwarding. When selected, CRC
is passed transparently from the Transmit Client
Interface to line and, is preserved on the
Received Client Interface.
False
TB_IPG_LEN Integer
Transmit Inter-Packet Gap. Defined, in Bytes,
the IPG between transmitted Frames.
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3.7 Design Implementation with Quartus II
Two TCL script (quartus.tcl) is provided in the design kit directory quartus, which performs
the following actions:
1. Create project
2. Build database
3. Set timing constraints
4. Set I/O Fast Register constraint on fast I/O signals
5. Run Quartus fitter
6. Reports design timing and timing violations
7. Generates VHO VHDL gate level netlist and SDO timing file used during Gate level
simulation
The TCL script can run from the Quartus II graphical interface or in batch mode.
• Graphical
Mode:
1. In Quartus II TCL console Change to Quartus working directory
cd <Design Kit Root>/quartus
2. Run the design TCL script
source quartus.tcl
3.8 VQM Netlist Generation
After you obtain a core license from Altera, a VQM netlist of the Core can be generated with the
Quartus II software. The VQM netlist can be used to integrate the Core in a customer design.
To create the VQM netlist:
1. Analyze and Synthesize the Core
2. Generate the VQM Netlist
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