Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY - Manual (Page 4)

Stratix II GX Embedded Gigabit Ethernet MAC / PHY
User's Guide
Version 1.0 - October 2005
2 Design Flow
The different steps of the Embedded Gigabit Ethernet MAC-PHY Design are:
• Core
generation
• RTL
Simulation
• Synthesis
• Implementation using Quartus II
• Gate-Level Simulation – Not available with Evaluation License
The design kit provides scripts for ease of use, fast design and verification / implementation turn-
around.
The tools primarily supported are:
• Simulation: Modelsim Version 5.7a or higher
• Synthesis: Altera Quartus II V5.1 or higher
• Implementation: Altera Quartus II V5.1 or higher
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