Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY - Manual (Page 5)

Stratix II GX Embedded Gigabit Ethernet MAC / PHY
User's Guide
Version 1.0 - October 2005
3 Generating the MAC/PHY Core
3.1 Overview
After the Core configuration utility is installed, start the utility and when the panel is available:
1. Select the Core options on the panel
2. Press the "Generate HDL" button.
3. A new window appears prompting you for a key. Type LbNH-sC79 and press “Enter”.
4. A new window appears which can be used to navigate through the file system to select
an existing directory or create a new working directory. After pressing the "open" button
finally creates the database.
VHDL
Design FILES
ModelSim ModelSim
Quartus Quartus
VHDL
Testbench
Constraint
Template
User Constraints
VHO SDF
Testbench
Configuration
MorethanIP TestBuilder
Simulation
Control
Figure 1: Design Flow Overview
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