Altera Stratix III - Manual (Page 19)

© August 2008 Altera Corporation Stratix III Development Kit User Guide
5. Power Measurement
Introduction
One of the main features of the Stratix III FPGA device is its low power consumption.
You can measure the power used by the 3SL150 FPGA device on the Stratix III
development board for various conditions with a power design example provided
with the kit.
With the power design example, you can control the amount of logic utilized in the
FPGA, the clock frequency, and the number of I/Os used, and measure the effect on
power used by the Stratix III device.
Power Design Example
The power design example uses a replicated module, stamp.v, that contains
combinational logic, randomly filled ROMs, multiplier blocks, and shift registers that
change with every clock cycle. The frequency and resource states indicated in
Table 5–2 and Table 5–3 on page 5–2 , respectively, represent the percent of full design
used. As compiled, the full example design uses the following FPGA resources:
■ Combinational adaptive look-up tables (ALUTs): 1,872 / 113,600 (2%)
■ Dedicated logic registers: 106,640 / 113,600 (94%)
■ Total registers: 106,640
■ Total pins: 173 / 744 (23%)
■ Total memory bits: 2,621,440 / 5,630,976 (47%)
■ Embedded multiplier 18-bit elements: 320 / 384 (83%)
■ Total PLLs: 1/8 (13%)
Table 5–1 describes the functionality of the four user push buttons that control the
power design example. The on-board 50-MHz oscillator provides the input clock
(i_clk, PIN_T33).
Table 5–1. Four Input Button Functionality
User Push
Button FPGA Pin Type Description
User_PB0 B17 Reset Resets the demo to the beginning, i_nrst
User_PB1 A17 Toggle Advances the design example to the next higher frequency, i_nfreq_next
User_PB2 A16 Toggle Advances the design example to the next higher resource utilization,
i_nperc_next
User_PB3 K17 Toggle Enables the outputs to toggle, i_noutput_ena