Parallel flash loader instantiation, Programming the flash device, Programming the flash – Altera Stratix III User Manual

Page 29

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Appendix A: Programming the Flash Device

A–3

Parallel Flash Loader Instantiation

© August 2008

Altera Corporation

Stratix III Development Kit User Guide

6. Click Generate.

Generation takes a short time and it is confirmed by a

“Generated… pof successfully” message.

You now have a successfully generated .pof that can be programmed to the flash
device to automatically configure the FPGA on your Stratix III development board.

Parallel Flash Loader Instantiation

The development kit includes a PFL megafunction design, stratixIII_3sl150_dev_pfl,

in the directory <path>\examples. The Quartus II software uses the PFL to write
programming files to the flash device, which then loads the FPGA on power up.

To write to a flash device, you must first program the PFL into the FPGA by using the
Quartus II software as described in

“Programming the Flash Device” on page A–3

,

steps

1

through

8

.

f

For more information about the PFL megafunction, refer to

AN 386: Using the Parallel

Flash Loader with the Quartus II Software

.

Programming the Flash Device

To program the flash device on the development board, you must first create a .pof
flash file as described in

“Creating a Flash File” on page A–1

. The following

procedure describes programming the PFL into the FPGA, then uses the PFL to write
the .pof flash file into the flash device.

To download a configuration bit stream into the flash device, perform the following
steps:

1. Ensure that the POWER switch SW4 is in the OFF (or DOWN) position.

2. Verify the switch SW1 and jumper settings shown in

Table 4–2 on page 4–3

.

3. Connect the USB cable to the USB port on the board.

4. Cycle the POWER switch OFF then ON.

5. On the Tools menu in the Quartus II software, click Programmer.

6. Click Add File and select

<path>\examples\stratixIII_3sl150_dev_pfl\stratixIII_3sl150_dev_pfl.sof.

7. Turn on the Program/Configure option for the added file.

8. Click Start to download the selected configuration file to FPGA (

Figure A–2

). The

FPGA is configured when the progress bar reaches 100%, after which it is ready to
access and program the flash device.

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