Altera Transceiver Signal Integrity - Manual (Page 25)

Chapter 6: Stratix IV GX Transceiver Signal Integrity Demonstration 6–7
Running the Demonstration Application and Test Designs
December 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition User Guide
PCI Express Tab
This tab is only available when signal_integrity_demo1.sof is loaded. It provides the
options to control PCI Express (PIPE) parameters for channels 3 and 4 in the middle
transceiver block. Turning on Switch to Gen2 data rate enables the hardware to
change channels 3 and 4 to Gen2 data rate and makes the following options available:
If you have selected the Switch to Gen2 data rate option, set the pre tap and
2ndpost
tap to 0 to meet the Gen 2 specification.
Power and Temperature Tab
The application displays the Stratix IV device junction temperature. It also shows the
power or current values for the six supply rails.
You can also observe the power and temperature values on the LCD. For more
information, refer to
“LCD Information” on page 6–2 .
The power values shown for the VCCA_L/R and the VCCH_GXB assumes that the
jumper settings are set to 3.0 V and 1.4 V, respectively. Click the Help button to see the
required jumper settings.
Channel Reconfig Tab
This tab is only available when signal_integrity_demo3.sof is loaded. You can
dynamically select the input reference clock from the socket clock input or an external
SMA clock input (J19 and J20). To receive the input clock from the external SMA, turn
on switch to SMA clock.
The serial data rate of each transceiver channel can be 16 times or 20 times the clock
rate. The Change Data Rate controls configure each transceiver block with one of the
following data rates:
5 Gbps — Configures the transceiver channel to run at 16 times the input reference
clock. If input reference clock is 312.5 MHz, the transceiver runs at 5 Gbps.
6.25 Gbps — Configures the transceiver channel to run at 20 times the input reference
clock. If input reference clock is 312.5 MHz, the transceiver runs at 6.25 Gbps.
Reverse serial 5G (Post CDR) — Configures the transceiver channel in reverse serial
loop back mode. In this configuration, the output of the RX CDR that is configured to
track serial data input at 16 times the input reference clock is looped to the transmitter
serializer. The serializer is clocked by the recovered clock generated by the RX CDR.
Data checkers are not available for this option.
Reverse serial 6.25G (Post CDR) — Configures the transceiver channel in reverse
serial loop back mode. In this configuration, the output of the RX CDR that is
configured to track serial data input at 20 times the input reference clock is looped to
the transmitter serializer. The serializer is clocked by the recovered clock generated by
the RX CDR. Data checkers are not available for this option.
Table 6–6.
Parameter Description
Txdeemphasis 0: –6 db; 1: –3.5 db
TxMargin 0–7