Altera Arria V GX FPGA Development Board - Manual (Page 57)

Chapter 2: Board Components 2–47
Components and Interfaces
November 2013 Altera Corporation Arria V GX FPGA Development Board
Reference Manual
36 HSMB_JTAG_TMS — 2.5-V CMOS JTAG mode select signal
37 HSMB_JTAG_TDO — 2.5-V CMOS JTAG data output
38 HSMB_JTAG_TDI — 2.5-V CMOS JTAG data input
39 HSMB_CLK_OUT0 AJ33 LVDS or 2.5-V Dedicated CMOS clock out
40 HSMB_CLK_IN0 AR6 LVDS or 2.5-V Dedicated CMOS clock in
41 HSMB_D0 AW25 2.5-V CMOS Dedicated CMOS I/O bit 0
42 HSMB_D1 AW26 2.5-V CMOS Dedicated CMOS I/O bit 1
43 HSMB_D2 AV25 2.5-V CMOS Dedicated CMOS I/O bit 2
44 HSMB_D3 AV24 2.5-V CMOS Dedicated CMOS I/O bit 3
47 HSMB_TX_D_P0 AC29 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4
48 HSMB_RX_D_P0 AC25 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5
49 HSMB_TX_D_N0 AB29 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6
50 HSMB_RX_D_N0 AB25 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7
53 HSMB_TX_D_P1 AE28 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8
54 HSMB_RX_D_P1 AF25 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9
55 HSMB_TX_D_N1 AD28 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10
56 HSMB_RX_D_N1 AE25 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11
59 HSMB_TX_D_P2 AE29 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12
60 HSMB_RX_D_P2 AD27 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13
61 HSMB_TX_D_N2 AD29 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14
62 HSMB_RX_D_N2 AC27 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15
65 HSMB_TX_D_P3 AK27 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16
66 HSMB_RX_D_P3 AB28 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17
67 HSMB_TX_D_N3 AJ27 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18
68 HSMB_RX_D_N3 AB27 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19
71 HSMB_TX_D_P4 AL29 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20
72 HSMB_RX_D_P4 AJ28 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21
73 HSMB_TX_D_N4 AK29 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22
74 HSMB_RX_D_N4 AH28 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23
77 HSMB_TX_D_P5 AL30 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24
78 HSMB_RX_D_P5 AG28 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25
79 HSMB_TX_D_N5 AK30 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26
80 HSMB_RX_D_N5 AF28 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27
83 HSMB_TX_D_P6 AL32 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28
84 HSMB_RX_D_P6 AH30 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29
85 HSMB_TX_D_N6 AK32 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30
86 HSMB_RX_D_N6 AG30 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31
89 HSMB_TX_D_P7 AM31 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32
Table 2–46. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference (J2) Schematic Signal Name
Arria V GX
FPGA
Pin Number
I/O Standard Description