Altera Arria V GX FPGA Development Board - Manual (Page 80)

2–70 Chapter 2: Board Components
Memory
Arria V GX FPGA Development Board November 2013 Altera Corporation
Reference Manual
M10 QDRII_Q1 AT24 1.8-V HSTL Read data bus
L11 QDRII_Q2 AU24 1.8-V HSTL Read data bus
K11 QDRII_Q3 AL24 1.8-V HSTL Read data bus
J10 QDRII_Q4 AE24 1.8-V HSTL Read data bus
F11 QDRII_Q5 AF24 1.8-V HSTL Read data bus
E11 QDRII_Q6 AH24 1.8-V HSTL Read data bus
C10 QDRII_Q7 AW23 1.8-V HSTL Read data bus
B11 QDRII_Q8 AW24 1.8-V HSTL Read data bus
P9 QDRII_Q9 AP24 1.8-V HSTL Read data bus
N9 QDRII_Q10 AT23 1.8-V HSTL Read data bus
L10 QDRII_Q11 AU23 1.8-V HSTL Read data bus
K9 QDRII_Q12 AP23 1.8-V HSTL Read data bus
G9 QDRII_Q13 AD22 1.8-V HSTL Read data bus
F10 QDRII_Q14 AE23 1.8-V HSTL Read data bus
E9 QDRII_Q15 AL23 1.8-V HSTL Read data bus
D9 QDRII_Q16 AT22 1.8-V HSTL Read data bus
B10 QDRII_Q17 AU22 1.8-V HSTL Read data bus
B2 QDRII_Q18 AW22 1.8-V HSTL Read data bus
D3 QDRII_Q19 AV21 1.8-V HSTL Read data bus
E3 QDRII_Q20 AW21 1.8-V HSTL Read data bus
F2 QDRII_Q21 AH23 1.8-V HSTL Read data bus
G3 QDRII_Q22 AE22 1.8-V HSTL Read data bus
K3 QDRII_Q23 AF22 1.8-V HSTL Read data bus
L2 QDRII_Q24 AP22 1.8-V HSTL Read data bus
N3 QDRII_Q25 AW19 1.8-V HSTL Read data bus
P3 QDRII_Q26 AW20 1.8-V HSTL Read data bus
B1 QDRII_Q27 AH22 1.8-V HSTL Read data bus
C2 QDRII_Q28 AT20 1.8-V HSTL Read data bus
E1 QDRII_Q29 AU20 1.8-V HSTL Read data bus
F1 QDRII_Q30 AK21 1.8-V HSTL Read data bus
J2 QDRII_Q31 AU19 1.8-V HSTL Read data bus
K1 QDRII_Q32 AV19 1.8-V HSTL Read data bus
L1 QDRII_Q33 AN21 1.8-V HSTL Read data bus
M2 QDRII_Q34 AE21 1.8-V HSTL Read data bus
P1 QDRII_Q35 AG21 1.8-V HSTL Read data bus
A8 QDRII_RPSN AR25 1.8-V HSTL Read port select
A4 QDRII_WPSN AK24 1.8-V HSTL Write port select
Table 2–58. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board
Reference (U8)
Schematic
Signal Name
Arria V GX FPGA
Pin Number
I/O Standard Description