Artesyn ATCA-7368 Installation and Use (June 2014) - Manual (Page 88)

Functional Description
ATCA-7368 Installation and Use (6806800M12D) 88
5.5 Chipset
The Xeon 5520 (Tylersburg IOH36 D) provides the interface between the processor Intel
QuickPath Interconnect and industry-standard PCI Express components. The two Intel
QuickPath Interconnect interfaces are full-width links (20 lanes in each direction). Xeon 5520
(Tylersburg IOH36 D) provides 36 PCI-e Gen2 Ports organized in three groups of 16, 16 and 4
PCI-e entities. The x16 PCIe Gen2 entities are also configurable as x8 and x4 links. In addition,
the legacy Xeon 5520 (Tylersburg IOH36 D) supports an x4 ESI link interface (Enterprise South
Bridge Interface) which connect to the Southbridge ICH10. The ESI is similar to an x4 PCI-
express interface. The following figure gives an overview of the Xeon 5520 (Tylersburg IOH36
D) features.
5.6 I/O Controller
The ICH10R provides extensive I/O interface support and the boot path to SPI Boot Flash
devices for the processor. ICH10R is connected to the system through the Enterprise
Southbridge Interface (ESI) of the Xeon 5520 chipset.
The following is a list of the main internal features and the I/O interface functions provided by
the ICH10R Southbridge.
 Six x4 PCI Express 1.1 interface
 LPC interface
 SPI interface (Boot Flash): up to two devices 20 + 33 MHz
 Six serial ATA (SATA) interfaces
 Twelve USB 2.0 interfaces
 Two 8259 interrupt controllers and I/O APIC controllers
 Integrated I/O APIC
 Power management support
 Two 8237 DMA controller
 8254-based Counter Timer/timers
 High-precision Event timers (HPET)
 RTC with 256-byte battery-backed SRAM