Sundance SMT364 - Manual (Page 10)

Version 1.0 Page 10 of 37 SMT364 User Manual
Most of the resources are not used by the default firmware, which allows the user to
implement some extra processing such as digital filters.
ADCs.
The SMT364 is populated with four AD6645s . For more details about these
converters (inner characteristics), please refer to the manufacturer (Analog Devices)
datasheets.
Data and control lines of the converters are all connected to the FPGA.
Clock management.
The SMT364 has two identical on-board low-jitter clock synthesizers, one per pair of
ADCs. Both have a Serial Port Interface. The FPGA is responsible for setting them to
the correct values loaded into a control register. A wide range of frequencies can be
set this way. The SPIs are write-only, i.e. they can’t be read back.
Clock multiplexers are also available on the board to route the appropriate clock
signal (from external or on-board source) to the converters. It is usual to have both
ADCs fed with the same sampling clock but it is possible to have an ADC receiving
the external clock and the second one receiving the on-board clock. In this particular
case, two 16-bit interfaces are necessary to transfer samples to an external TIM.
Sundance High-speed Bus - SHB.
The SMT364 provides 2 full SHB (Sundance High-speed Bus) connectors, labelled
SHBA (J2) and SHBB (J3) – see Figure 8 - Connector Location.)
SHBA and SHBB are set as transmitter only to transfer data coming from the
Analogue-to-Digital Converters to an external SHB module, for instance SMT365,
SMT365E or SMT374. Transfers at up to 100 MHz are supported on these two SHB
connectors.
The FPGA routes the data lines coming from ADCA and ADCB to SHBA and from
ADCC and ADCD to SHBB. The board offers to possibility to output data in either
two’s complement or binary format. It is also possible to output a 16-bit counter on
each SHB half for system testing purpose – It then becomes easier to detect any
missing data. The board can also be enabled to add channels with each other
ADCA+ADCB and/or ADCC+ADCD and/or ADCA+ADCB+ADCC+ADCD in binary
format only.
On each data path, decimators can be set to trim samples out. Decimators are
independent. If both decimators of a pair of channel (channels A and B or Channels
C and D) are set with the same values and if the sampling clocks (Channel A and
Channel B or Channel C and Channel D) are the same, data streams of a same SHB
connector can be considered as synchronised and therefore the two 16-bit data
streams can be considered as a single 32-bit data stream.
It is possible to control (start/stop) the data flow by the way of an external trigger, for
which the active level (high or low) can be set in a control register. It is recommended