Sundance SMT395 - Manual (Page 11)

Version 1.1.7 Page 11 of 26 SMT395 User Manual
SDRAM
256Mbytes of SDRAM is available (4 devices of 64M bytes, Samsung K4S511632M-
TC75) The SDRAM operates at EMIF clock speed. It is typically 133MHz for the
SMT395.
FLASH
An 8Mbyte flash memory is provided with direct access by the DSP. This device
contains boot code for the DSP and the configuration data for the FPGA.
This is a 16-bit wide device.
The flash device can be re-programmed by the DSP at any time. There is a software
protection mechanism to stop most errant applications from destroying the device’s
contents.
Note that the flash memory is connected as a 16 bit device, but during a C6x boot
(internal function of the C6x) only the bottom 8 bits are used.
As the C60 only provides 20 address lines on its EMIFB, two GPIO lines (9 and 10)
are used to access this device. So the device should be seen as divided in 4x
2MBytes pages.
FLASH Paging
Selecting the visible flash memory page (4 pages of 2Mbytes) involves setting up the
GPIO registers bit 9 and 10. Make sure that the setup of the other GPIO is kept
untouched as they are used for external interrupt and leds.
Virtex-II Pro FPGA
This device, either a Xilinx XC2VP20 or 30, is responsible for the provision of the
SHBs, RSLs, 6 comm ports and the global bus. On power-up, this device is un-
configured (SRAM based FPGA technology). During the DSP boot process, the
FPGA is configured for normal operation.
The standard configuration for the primary FPGA uses approximately 3800 slices and
128 dual port rams. The remainder can be used for additional functionality.
Note that the ComPorts and global bus interfaces provided by the FPGA are 5V
tolerant and can thus be interfaced with older systems using the ‘C40 based modules
and TIM carriers.
All of the external interfaces provided by the FPGA are fully described in the
SMT6400 help file.
The Sundance High-speed BUS (SHB) specification can be found here .