Sundance SMT395 - Manual (Page 12)

Version 1.1.7 Page 12 of 26 SMT395 User Manual
The SDL specification can be found here .
The RSL specification (Xilinx Rocket IO) can be found here .
The FPGA configuration is done in two steps:
First asserting the prog line clears the FPGA configuration. This is simply done by an
access in EMIFB CE2.
Then after the FPGA configuration has cleared the FPGA configuration is
programmed serially by writing the data from the flash in EMIFB CE3.
At the end of the programming a register is polled to wait until the FPAG is
configured and proceed with the application loading process.
External Clock
An external clock input is provided to the FPGA. This signal is directly connected to
the secondary TIM connector user defined pin 12.
Version control
Version number for FPGA firmware and boot code is stored in the Flash ROM during
programming as zero-terminated ASCII strings. These are displayed when using the
SMT6001 utility.
Reprogramming the firmware and boot code
The reprogramming of the module is done using the SMT6001.
It contains the latest boot code and FPGA firmware for it and allows storing a user
application in it.