Fpga resources, Interrupts, Communication ports – Sundance SMT395 User Manual
Page 13: Sdb clock selection, Global bus, Config & nmi
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SMT395 User Manual
FPGA resources
Interrupts
Communication ports
The SMT395 provides 6 ComPorts. They are ComPort 0, 1, 2, 3, 4 and 5.
SDB
The SMT395 provides two SHB which are 32-bit SDB.
They are numbered SDB0 for SHBA, SDB1 for SHBB.
SDB Clock selection
The SDB clock selection is not implemented. The clock is running at the EMIF speed
i.e. 133MHz.
RSL
This interface is still under test. It needs to be standardized across the Sundance
module range.
The status so far:
-5 FPGA are limited to 2Gbit/s serial links (see Xilinx datasheet).
-6 FPGA theoretical limit is 3.125Gb/s. This hasn’t been verified on the hardware yet.
Tests have been performed with aurora protocol with on-board 100MHz clock. A
single lane solution gives around 170MB/s between DSPs. The first tests on the 4
lanes interface have been performed and we are evaluating the best architecture.
The board also includes a differential oscillator (EG-2121CA LV-PECL) for faster
speed rate.
The interface is not fixed and not provided yet.
Global bus
The SMT395 provides one global bus interface.
CONFIG & NMI