Sundance SMT395 - Manual (Page 9)

Version 1.1.7 Page 9 of 26 SMT395 User Manual
Boot Mode
The SMT395 is configured to boot from flash after a reset
Flash Boot
1. The processor copies a bootstrap program from the first part of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT395 then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance High-speed Buses.
This step must have been completed before data can be sent to the ComPorts
from external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the six
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports. See “Application Development” for details of the boot
loader format;
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around 1s for a SMT395.
A typical time to wait after releasing the board reset should be in excess of this
delay, but no damage will result if any of the I/Os are used before they are fully
configured. In fact, the comm. Ports will just produce a not ready signal when data
is attempted to be transferred during this time, and then continue normally after
the FPGA is configured.